Continuous scaling of integrated circuits has made circuits increasingly susceptible to variations. These variations can erode timing windows, and eventually contribute to circuit failure. This has resulted in increasing interest in statistical modeling techniques that can be used to enable statistical analysis and optimization of circuit designs.
Sampling based statistical timing analysis is prohibitively expensive and difficult to construct. An efficient but still pessimistic approach known as on-chip variations (OCV) approach uses timing-derating factors on gate and wire delays. OCV imposes unrealistic performance penalty on the circuit designs. A less pessimistic approach known as parametric on chip variation (POCV) assigns each gate delay the standard deviation of its change. Hence, the probability density functions (pdf) of the gate delays are always assumed Gaussian.
The Gaussian is a poor assumption for capturing the shapes of gate delay distributions. The reason is that any Gaussian distribution has zero skewness so if the distribution of the delay through the gate is skewed, this skewness will not be captured by any Gaussian distribution. Also, the Gaussian distribution has zero peakedness (kurtosis) so it cannot capture the peakedness of the distribution. Therefore, the POCV approach cannot accurately capture the shapes of gate delay distributions. Moreover, in order to maintain the presumed Gaussian assumption, a crude approximation is applied to the maximum operation which results in pessimistic mean and standard deviation.